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general description the max7651/max7652 are complete 12-bit data-acqui- sition systems featuring an algorithmic, switched-capaci- tor, analog-to-digital converter (adc), a pulse- width-modulated digital-to-analog converter (dac), three timer/counters, and an industry-standard 8051 micro- processor core with a variety of i/o peripherals. power- down capability and full functionality with supply voltages as low as +3v make the max7651/max7652 suitable for portable and power-sensitive applications. the max7651/max7652 perform fully differential voltage measurements with 12-bit resolution, programmable gain, and separate track-and-hold for both positive and nega- tive inputs. the converter accepts versatile input modes consisting of four 2-channel signal pairs or eight 1-chan- nel signals relative to a floating common. the max7651/max7652 microprocessor systems feature a cpu, 256 bytes of ram, two 8kb flash memory, four 8-bit i/o ports, two uarts, an interrupt controller, and a watchdog timer. only four clock cycles are required to complete each microprocessor instruction. the max7651/max7652 are available in 64-pin tqfp packages. applications hand-held instruments portable data-acquisition systems temperature controllers smart transmitters data loggers multi-channel data-acquisition with data formatting features 12-bit 53ksps adc with fully differential inputs dual 8-bit pwm dac outputs three timers 4-clock cycle 8051-compatible instruction set with dual data pointers programmable watchdog supervisor four parallel i/o ports dual serial i/o ports (up to 375kb) +3v or +5v single-supply operation dc to 12mhz clock speed 64-pin tqfp package max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ________________________________________________________________ maxim integrated products 1 256 bytes ram watchdog timer serial port 0 txd rxd 8k byte flash 2000h 3fcoh serial port 1 txd rxd int0 ext mem timer 0 timer 1 timer 2 t0 t1 t2 t2_out t2_out pwma output pwmb output int1 ain0 ain7 analog inputs ref+ ref- four 8-bit i/o ports 8k byte flash 0000h 1fffh pulse- width modulator memory address and data buses sfr bus 12-bit a/d converter interrupt controller 8051 cpu upper lower max7651 max7652 acom functional diagram 19-2119; rev 0; 8/01 ordering information part temp. range pin-package max7651 ccb 0 c to +70 c 64 tqfp max7651ecb -40 c to +85 c 64 tqfp max7652 ccb 0 c to +70 c 64 tqfp max7652ecb -40 c to +85 c 64 tqfp pin configuration appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (max7651 av dd = v pwmv = dv dd = v ref+ = +4.5v to +5.5v, v ref - = 0, f xtal = 12mhz. max7652 av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, a com = a vdd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , pwmv, dv dd to agnd_ ..............................-0.3v to +6v av dd , dv dd to dgnd..............................................-0.3v to +6v av dd to dv dd .......................................................-0.3v to +0.3v agnd, pwmg to dgnd .......................................-0.3v to +0.3v analog inputs (ain_, acom, xtal1, xtal2) to agnd................................................-0.3v to av dd_ + 0.3v analog outputs (pwma, pwmb) to agnd_..............................................-0.3v to av dd_ + 0.3v digital i/o (a_, ad_, ale/ prog , ea /v pp , int0 , int1 , p_._, psen , rst) to dgnd ..........-0.3v to dv dd + 0.3v ref+, ref- to agnd_ ..............................-0.3v to av dd_ + 0.3v short-circuit duration (pwm_, p_._, ale/ prog , psen )..........1s continuous power dissipation (t a = +70?) 64-pin tqfp (derate 5.00mw/? above +70?).........500mw operating temperature range max765_ccb ....................................................0? to +70? max765_ecb .................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution res 12 bits max7651 1.5 differential max7652 1.0 max7651 4.0 rel ati ve accur acy ( n ote 1) inl single-ended max7652 1.5 lsb differential 0.5 1 differential nonlinearity (note2) dnl single-ended 0.5 1 lsb offset error (note 2) 2.3 7 lsb offset temperature coefficient 0.25 lsb/ c gain error (note 2) 3% gain temperature coefficient 3 ppm/ c channel-to-channel matching (note 2) offset and gain 0.25 lsb dynamic specifications (53ksps, 1khz sine-wave input, 5vp-p (max7651), 2.5vp-p (max7652)) differential 71 signal-to-noise + distortion sinad single-ended 67 db differential -78 total harmonic distortion thd all unaliased harmonics single-ended -73 db differential 81 spurious-free dynamic range sfdr single-ended 79 db channel-to-channel crosstalk (note 3) -85 db small-signal bandwidth -3db rolloff 1 mhz full-power bandwidth 1 mhz
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems _______________________________________________________________________________________ 3 electrical characteristics (continued) (max7651 av dd = v pwmv = dv dd = v ref+ = +4.5v to +5.5v, v ref - = 0, f xtal = 12mhz. max7652 av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, a com = a vdd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units conversion rate conversion time t conv f xtal = 12mhz 18.7 s conversion rate f xtal = 12mhz 53.6 ksps analog inputs (ain0?in7, acom) input voltage range 0av dd v common-mode range 0av dd v input current 1a input capacitance c in 10 pf digital inputs input voltage low v il -0.5 0.2 x (dv dd - 1) v input high voltage, except xtal and rst 0.2 x (dv dd + 0.9) dv dd + 0.5 input voltage high v ih input high voltage, xtal and rst 0.7 x (dv dd + 0.1 dv dd + 0.5 v max7651 90 409 internal reset pulldown resistance r rst max7652 170 490 k ? logical high-to-low transition current i tl guaranteed by design 750 a log i cal z er o inp ut c ur r ent, p or ts 1, 2, and 3 ale , psen (note 4) 75 a input leakage current, port 0 i in v in = dv dd or dgnd 10 a input capacitance 10 pf digital outputs output low voltage v ol i sink = 4ma 0.45 v max7651: i source = 4ma 2.4 output high voltage v oh max7652: i source = 2ma 2.4 v
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 4 _______________________________________________________________________________________ electrical characteristics (continued) (max7651: av dd = v pwmv = dv dd = v ref+ = +4.5v to +5.5v, v ref - = 0, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, a com = a vdd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units external voltage reference characteristics (ref+, ref-) reference voltage range v ref+ - v ref- 0av dd v reference input current 35 a reference input capacitance 10 pf power requirements analog supply current 5ma max7651, during page erase 55 digital supply current max7652, during page erase 40 ma max7651 13 30 idle-mode digital supply current max7652 5 12 ma stop-mode supply current i avdd + i dvdd (note 5) 10 a analog power-supply rejection ratio psrr -40 db pwm outputs output low voltage i sink = 2ma 0.4 v output high voltage i source = 2ma 2.4 v flash external programming (figure 1, note 6) program pulse width t progl 10t ck ns program address and data setup t asuw guaranteed by design 3t ck ns max7651 7t ck + 54000 16t ck + 72000 program cycle time t write max7652 7t ck + 54000 32t ck + 72000 ns verify address and data set t adsur 3t ck ns verify access time t read 9t ck + 50 ns minimum p2.7 pulse width low t p27l 10t ck ns minimum p2.7 pulse width high t p27h guaranteed by design 3t ck ns clock period t ck 83 250 ns flash external mass erase (figure 2, note 6) erase mode setup t p23su 3t ck ns program pulse width t eraslow 10t ck ns erase cycle time t m ass e ras e 8.29 11 ms
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems _______________________________________________________________________________________ 5 timing characteristics (max7651: av dd = v pwmv = dv dd = v ref+ = +4.5 to +5.5v, v ref- = 0, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, acom = av dd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (figure 3) parameter symbol conditions min typ max units rst pulse width (high) 100 + (64 x t ck ) s external clock clock frequency f ck 12 mhz clock period t clcl 83 ns clock high time t chcx 25 ns clock low time t clcx 25 ns clock rise time t clch guaranteed by design 10 ns clock fall time t chcl guaranteed by design 10 ns instruction timing characteristics ale pulse width t lhll 1.5t clcl - 20 ns address valid to ale low t avll 0.5t clcl - 15 ns address hold after ale low t llax 0.5t clcl - 20 ns ale low to valid instruction in t lliv 2.5t clc l - 35 ns ale low to psen low t llpl 0.5t clcl - 10 ns psen pulse width t plph 2t clcl - 15 ns psen low to valid instruction in t pliv 2t clcl - 35 ns input instruction hold after psen t pxix 0ns input instruction float after psen t pxiz t clcl - 15 ns address to valid instruction in t aviv 3t clcl - 50 ns psen low to address float t plaz 10 ns
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 6 _______________________________________________________________________________________ timing characteristics (continued) (max7651: av dd = v pwmv = dv dd = v ref+ = +4.5 to +5.5v, v ref- = 0, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, acom = av dd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (figure 3) parameter symbol conditions min typ max units movx timing characteristics (note 6) t mcs = 0, guaranteed by design 2t clcl - 20 rd pulse width t rlrh t mcs > 0, guaranteed by design t mcs - 20 ns t mcs = 0 2t clcl - 20 wr pulse width t wlwh t mcs > 0 t mcs - 20 ns t mcs = 0 2t clcl - 55 rd low to valid data in t rldv t mcs > 0 t mcs - 55 ns data hold after rd t rhdx 0ns t mcs = 0 t clcl - 10 data float after rd t rhdz t mcs > 0 2t clcl - 10 ns t mcs = 0 2.5t clcl - 58 ale low to valid data in t lldv t mcs > 0 1.5t clcl - 58 + t mcs ns t mcs = 0 3t clcl - 60 port 0 address to valid data in t avdv1 t mcs > 0 2t clcl - 61 + t mcs ns t mcs = 0 3t clcl - 60 port 2 address to valid data in t avdv2 t mcs > 0 2t clcl - 64 + t mcs ns t mcs = 0 0.5t clcl - 5 0.5t clcl + 10 ale low to rd or wr low t llwl t mcs > 0 1.5t clcl - 5 1.5t clcl + 10 ns t mcs = 0 t clcl - 10 port 0 address valid to rd or wr low t avwl1 t mcs > 0 2t clcl - 10 ns t mcs = 0 t clcl - 10 port 2 address valid to rd or wr low t avwl2 t mcs > 0 2t clcl - 10 ns
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems _______________________________________________________________________________________ 7 timing characteristics (continued) (max7651: av dd = v pwmv = dv dd = v ref+ = +4.5 to +5.5v, v ref- = 0, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = +2.7v to +3.6v, v ref+ = +2.5v, v ref- = 0, acom = av dd /2, f xtal = 12mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (figure 3) parameter symbol conditions min typ max units t mcs = 0 -9 data valid to wr transition t qvwx t mcs > 0 t clcl - 12 ns t mcs = 0 2t clcl - 20 data valid before wr high t qvwh t mcs > 0 t mcs - 30 ns t mcs = 0 t clcl - 18 data hold after wr high t whqx t mcs > 0 2t clcl - 18 ns rd low to address float t rlaz 0ns t mcs = 0 0 10 rd or wr high to ale high t whlh t mcs > 0 t clcl - 5 t clcl + 11 ns serial port timing characteristics sm2 = 0 (12 clocks/cycle) 12 t clcl serial port clock cycle time t xlxl sm2 = 1 (4 clocks/cycle) 4 t clcl ns sm2 = 0 (12 clocks/cycle) 10 t clcl output data setup to clock rising edge t qvxh sm2 = 1 (4 clocks/cycle) 3 t clcl ns sm2 = 0 (12 clocks/cycle) 2 t clcl output data hold after clock rising edge t xhqx sm2 = 1 (4 clocks/cycle) t clcl ns sm2 = 0 (12 clocks/cycle) t clcl input data hold after clock rising edge t xhdx sm2 = 1 (4 clocks/cycle) t clcl ns sm2 = 0 (12 clocks/cycle) 11t clcl clock rising edge to input data valid t xhdv sm2 = 1 (4 clocks/cycle) 3t clcl ns note 1: relative accuracy is the deviation of the analog value at any code from its theoretical value after the offset and gain errors have been nullified. note 2: a vdd = +5.0v, (v ref +) - (v ref -) = +5.0v or a vdd = +3.0v, (v ref +) - (v ref -) = +2.5v. note 3: ground at on channel; 10khz sine-wave applied to all off channels. note 4: ale and psen are in reset cycle. note 5: all digital inputs are at dgnd or dv dd . f xtal = 0. note 6: table 1. data memory stretch values. note 7: the minimum frequency when writing to the internal flash is 4mhz.
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 8 _______________________________________________________________________________________ note 1: to program the lock bits, ale must be low for duration of write lockbit cycle. note 2: int0 and int1 are open-drain and must either be driven or require a pullup (typically 10k ? ) to dv dd . md2 md1 md0 memory cycles read/write strobe width (clocks) strobe width time at 12mhz t mcs 0 0 0 2 2 167ns 0t clcl 0 0 1 3 (default) 4 334ns 4t clcl 0 1 0 4 8 668ns 8t clcl 0 1 1 5 12 997ns 12t clcl 1 0 0 6 16 1330ns 16t clcl 1 0 1 7 20 1666ns 20t clcl 1 1 0 8 24 2000ns 24t clcl 1 1 1 9 28 2333ns 28t clcl mode rst psen ale/ prog ea /v pp p2.6 p2.7 p3.6 p3.7 p2.5 write lower flash h l h lhhh l read lower flash h l h h l hh l write lock bit 1 h l h hhhhh write lock bit 2 h l hhhllh write lock bit 3 h l h hlhlh mass erase h l h hlllh read sig bytes h l h h l llll write upper flash h l h lhhhh read upper flash h l h h l hhh table 1. data memory stretch values table 2. external flash programming modes
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems _______________________________________________________________________________________ 9 ale/ ~prog p3.6 p3.7 p2.6 p2.5 p3.4 (ready/~bsy) p2.7 ~psen ~ea/v pp programming t eraslow t p23su 3t ck (min) (logic 1 ) t masserase figure 1. flash external mass erase waveforms
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 10 ______________________________________________________________________________________ ale port 0 port 2 psen t pxiz t llax t plph t pliv t llpl t plaz address a8 a15 out address a8 a15 out instruction in address a0 a7 address a0 a7 t aviv t lhll t avll t lliv t pxix figure 3a. external program memory read cycle p1.0 p1.7 92.0 p2.4 p2.5 lower = l upper = h p3.4 (ready/~bsy) p2.7 (read cycle) ale/~prog port 0 t adsur t read t write t p27h 3t ck (min) programming address verification address data in (logic 1 ) data out t p27l 10t ck (min) t adsuw 3t ck (min) t progl ea/vpp figure 2. flash external programming and verification waveforms
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 11 ale port 0 port 2 psen t whlh t rlrh t rldv t rlaz address a8 a15 out data in instruction in address a0 a7 address a0 a7 t avdv1 t avdv2 t llwl t lldv t rhd2 t rhdx rd figure 3b. external data memory read cycle ale port 0 port 2 wr psen t whlh t wlwh address a0 a7 address a0 a7 address a8 a15 out data out instruction in t avwl1 t avwl2 t whqx t qvwh t qvwx figure 3c. external program memory write cycle
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 12 ______________________________________________________________________________________ typical operating characteristics (t a = +25 c, unless otherwise noted.) max7651: av dd = v pwmv = dv dd = v ref+ = 5.0v, v ref- = 0, v com = av dd /2, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = v ref+ = 3.0v, v ref- = 0, v com = av dd /2, f xtal = 12mhz. -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 single-ended inl vs. output code max7651 toc01 code inl (lsb) 1500 2000 1000 500 0 -500 -1000 -1500 -2000 -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 -2000 -1000 -500 -1500 0 500 1000 1500 2000 dnl vs. output code max7651 toc02 code dnl (lsb) -0.6 -0.4 -0.5 -0.1 -0.2 -0.3 0.1 0.2 0 0.3 0 1500 2000 500 1000 2500 3000 3500 4000 4500 negative gain error vs. supply voltage max7651/2 toc03 code dnl (lsb) single-ended differential 1.0 0.5 0 -0.5 -1.0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 offset error vs. supplt voltage max7651/2 toc04 supply voltage (v) offset error (lsb) single-ended differential -0.7 -0.5 -0.6 -0.3 -0.4 -0.1 -0.2 0 -40 10 -15 35 60 85 offset error vs.temperature max7651 toc05 temperature ( c) offset error (lsb) differential single-ended 1.0 0.5 0 -0.5 -1.0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 positive gain error vs. supply voltage max7651 toc06 supply voltage (v) gain error (lsb) single-ended differential -0.8 -0.4 -0.6 0 -0.2 0.2 0.4 -40 10 -15 35 60 85 max7651 toc07 temperature ( c) gain error (lsb) single-ended differential positive gain error vs. temperature 0 0.4 0.2 0.8 0.6 1.2 1 1.4 .-40 10 -15 35 60 85 negative gain error vs. temperature max7651 toc08 temperature ( c) gain error (lsb) single-ended differential 5.000 4.950 4.900 4.850 0 4.800 2 1 345 pwm output high vs. source current max7651 toc09 source current (ma) pwm output high (v) av dd = 5v
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 13 3.000 2.950 2.900 2.850 2.800 02 1 345 pwm output high vs. source current max7651 toc10 source current (ma) pwm output high (v) av dd = 3v 0 50 150 100 200 250 02 1345 pwm output low vs. sink current max7651 toc11 sink current (ma) pwm output low (mv) av dd = 5v av dd = 3v 0 1 3 2 4 5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 analog supply current vs. input voltage max7651 toc12 input voltage (v) analog supply current (ma) 2.0 2.1 2.3 2.2 2.4 2.5 -40 0 -20 20 40 60 80 85 analog supply current vs. temperature max7651 toc13 temperature ( c) analog supply current (ma) av dd = 5v av dd = 3v 10.50 10.75 11.25 11.00 11.50 11.75 -40 10 -15 35 60 85 digital supply current vs.temperature max7651 toc14 temperature ( c) digital supply current (ma) 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 234 67891011 5 11213 digital supply current vs. clock frequency max7651 toc15 clock frequency (mhz) digital supply current (ma) 0 6 4 2 10 8 12 14 3.0 4.0 3.5 4.5 5.0 5.5 idle-mode supply current vs. input voltage max7651 toc16 input voltage ( v ) idle-mode supply current (ma) typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.) max7651: av dd = v pwmv = dv dd = v ref+ = 5.0v, v ref- = 0, v com = av dd /2, f xtal = 12mhz. max7652: av dd = v pwmv = dv dd = v ref+ = 3.0v, v ref- = 0, v com = av dd /2, f xtal = 12mhz. 0 1 3 2 4 5 3.0 4.0 3.5 4.5 5.0 5.5 power-down current vs. input voltage max7651 toc17 input voltage (v) power-down current ( a)
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 14 ______________________________________________________________________________________ pin description pin name function 1 ain0 analog input 0. negative differential input relative to ain1 or positive differential input relative to acom. (see table 6) 2 ain1 analog input 1. positive differential input relative to ain0 or positive differential input relative to acom. (see table 6) 3 ain2 analog input 2. negative differential input relative to ain3 or positive differential input relative to acom. (see table 6) 4 ain3 analog input 3. positive differential input relative to ain2 or positive differential input relative to acom. (see table 6) 5 ain4 analog input 4. negative differential input relative to ain5 or positive differential input relative to acom. (see table 6) 6 ain5 analog input 5. positive differential input relative to ain4 or positive differential input relative to acom. (see table 6) 7 ain6 analog input 6. negative differential input relative to ain7 or positive differential input relative to acom. (see table 6) 8 ain7 analog input 7. positive differential input relative to ain6 or positive differential input relative to acom. (see table 6) 9av dd positive analog supply voltage. analog power source for the a/d converter and other analog functions excluding the pwm d/a converter. bypass with a 0.1f in parallel with a 10f low esr capacitor to agnd. 10 agnd analog ground. connect pwmg to agnd. 11 ref+ high-side reference input. high-side reference voltage for a/d conversions. must be between av dd and agnd. bypass to agnd with a 0.1f in parallel with a 10f low esr capacitor to agnd. 12 ref- low- s i de refer ence inp ut. low - si d e r efer ence vol tage for a/d conversi ons. must b e betw een av d d and agn d . if not connected to agn d byp ass to agnd w ith a 0.1f in p ar al lel wi th a 10f low es r cap aci tor to agn d. 13 pwmv positive analog supply voltage 2. analog power source for the the pwm d/a converter outputs. bypass with a 0.1f in parallel with a 10f low esr capacitor to pwmg. 14 pwmg ground for pwm. connect to agnd. 15 pwma pwm output a. output of pwm d/a converter a. see pwm digital-to-analog conversions . 16 pwmb pwm output b. output of pwm d/a converter b. see pwm digital-to-analog conversions . 17 int0 external interrupt 0 input (active-low) 18 int1 external interrupt 1 input (active-low) p3.7: bit 7 for general purpose i/o port 3 (most significant bit) 19 p3.7/ rd rd : read output. read strobe for accessing external data memory (active-low) p3.6: bit 6 for general purpose i/o port 3 20 p3.6/ wr wr : write output. write strobe for writing to external data memory (active-low) p3.5: bit 5 for general purpose i/o port 3 21 p3.5/t1 t1: timer 1 external input p3.4: bit 4 for general purpose i/o port 3 t0: timer 0 external input 22 p3.4/t0/ ready ready: ready state output (external flash programming mode only) 23 p3.3 p3.3: bit 3 for general purpose i/o port 3 24 p3.2 p3.2: bit 2 for general purpose i/o port 3
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 15 pin description (continued) pin name function p3.1: bit 1 for general purpose i/o port 3 25 p3.1/ txd0 txd0: transmit serial output for serial port p3.0: bit 0 for general purpose i/o port 3 (least significant bit) 26 p3.0/ rxd0 rxd0: receive serial input for serial port 27 dgnd digital ground. connect dgnd to agnd at the power source. connect pins 27, 39, and 61 together. 28 dv dd positive digital supply voltage. bypass with a 0.1f in parallel with a 10f low esr capacitor to dgnd. connect pins 28, 40, and 62 together. p2.0: bit 0 for general purpose i/o port 2 (least significant bit) 29 p2.0/a8 a8: bit 8 for internal flash memory address p2.1: bit 1 for general purpose i/o port 2 30 p2.1/a9 a9: bit 9 for internal flash memory address p2.2: bit 2 for general purpose i/o port 2 31 p2.2/a10 a10: bit 10 for internal flash memory address p2.3: bit 3 for general purpose i/o port 2 32 p2.3/a11 a11: bit 11 for internal flash memory address p2.4: bit 4 for general purpose i/o port 2 33 p2.4/a12 a12: bit 12 for internal flash memory address p2.5: bit 5 for general purpose i/o port 2 34 p2.5 upper and lower internal flash memory select (see table 2) p2.6: bit 6 for general purpose i/o port 2 35 p2.6 flash programming mode select (see table 2) p2.7: bit 7 for general purpose i/o port 2 (most significant bit) 36 p2.7 flash programming mode select (see table 2) 37 psen program store enable (active-low). qualifies program read from external devices. to ensure flash data integrity during rst insertions, r load must be greater than or equal to 200k ? . ale: address latch enable. to ensure flash data integrity during rst insertions, r load must be greater than or equal to 200k ? . 38 ale/ prog prog : flash memory program pulse 39 dgnd digital ground. connect pins 27, 39, and 61 together. 40 dv dd positive digital supply voltage. bypass with a 0.1f in parallel with a 10f low esr capacitor to dgnd. connect pins 28, 40 and 62 together. p0.0: bit 0 for general purpose i/o port 0 (least significant bit) 41 p0.0/ad0 ad0: bit 0 for internal flash memory data or external memory i/o data (least significant bit) p0.1: bit 1 for general purpose i/o port 0 42 p0.1/ad1 ad1: bit 1 for internal flash memory data or external memory i/o data p0.2: bit 2 for general purpose i/o port 0 43 p0.2/ad2 ad2: bit 2 for internal flash memory data or external memory i/o data p0.3: bit 3 for general purpose i/o port 0 44 p0.3/ad3 ad3: bit 3 for internal flash memory data or external memory i/o data p0.4: bit 4 for general purpose i/o port 0 45 p0.4/ad4 ad4: bit 4 for internal flash memory data or external memory i/o data
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 16 ______________________________________________________________________________________ pin description (continued) pin name function p0.5: bit 5 for general purpose i/o port 0 46 p0.5/ ad5 ad5: bit 5 for internal flash memory data or external memory i/o p0.6: bit 6 for general purpose i/o port 0 47 p0.6/ ad6 ad6: bit 6 for internal flash memory data or external memory i/o p0.7: bit 7 for general purpose i/o port 0 (most significant bit) 48 p0.7/ ad7 ad7: bit 7 for internal flash memory data or external memory i/o p1.0: bit 0 for general purpose i/o port 1 (least significant bit) t2: timer 2 external input t2out: timer 2 external output 49 p1.0/t2/ t2out/ ad0 ad0: bit 0 for internal flash memory address p1.1: bit 1 for general purpose i/o port 1 t2ex: timer 2 external capture/reload trigger 50 p1.1/ t2ex/ ad1 ad1: bit 1 for internal flash memory address p1.2: bit 2 for general purpose i/o port 1 rxd1: receive serial input for uart 1 51 p1.2/ rxd1/ ad2 ad2: bit 2 for internal flash memory address p1.3: bit 3 for general purpose i/o port 1 txd1: transmit serial input for uart 1 52 p1.3/ txd1/ ad3 ad3: bit 3 for internal flash memory address p1.4: bit 4 for general purpose i/o port 1 53 p1.4/ ad4 ad4: bit 4 for internal flash memory address p1.5: bit 5 for general purpose i/o port 1 54 p1.5/ ad5 ad5: bit 5 for internal flash memory address p1.6: bit 6 for general purpose i/o port 1 55 p1.6/ ad6 ad6: bit 6 for internal flash memory address p1.7: bit 7 for general purpose i/o port 1 56 p1.7/ ad7 ad7: bit 7 for internal flash memory address ea : connect to dgnd to use external rom. connect ea to dv dd for internal flash memory. 57 ea /v pp v pp : flash programming voltage (external flash programming mode only) 58 rst active high reset. connected to an internal 130k ? pulldown resistor. connect a 2.2f (typ) capacitor from dv dd to rst. 59 xtal2 clock output. connect a crystal across xtal1 and xtal2. the on-chip clock signal is not available at xtal2. leave xtal2 unconnected when xtal1 is driven with an external clock. 60 xtal1 clock input. connect a crystal across xtal1 and xtal2. alternatively, drive xtal1 with a cmos- compatible clock and leave xtal2 unconnected. 61 dgnd digital ground. connect pins 27, 39, and 61 together. 62 dv dd positive digital supply voltage. bypass with a 0.1f in parallel with a 10f low esr capacitor to dgnd. connect pins 28, 40 and 62 together. 63 test test point. must be connected to dgnd. 64 acom analog common input. negative differential input relative to ain_ for single-ended measurements (see table 6). connect to av dd /2 for maximum input range.
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 17 detailed description max7651/max7652 architecture the max7651/max7652 are complete 12-bit data- acquisition systems featuring an algorithmic, switched- capacitor, analog-to-digital converter (adc), dual pulse-width-modulated digital-to-analog converter (dac), and an industry-standard 8051 microprocessor core with a variety of i/o and timing peripherals. using an external oscillator with an operating frequency between 1mhz and 12mhz, the max7651/max7652 execute the majority of its commands in only four clock periods to yield an average speed improvement of 2.5 times over typical 8051 microprocessors requiring 12 clock periods instructions. see the max7651/max7652 programmer s reference manual for further details. on-chip peripherals include four 8-bit parallel ports, two serial ports, three general-purpose timers, and a watchdog timer. the max7651/max7652 also feature 16kb in two banks of 8kb flash memory and 256 bytes of high-speed random access memory. memory organization the max7651/max7652 support up to 64kb of external program (read-only) memory and data (random- access) memory in conformance with the 8051 industry standard. figure 4 shows the program memory organization. when ea is high, the cpu has access to two internal 8kb blocks of flash memory beginning at addresses 0000h (lower block) and 2000h (upper block). addresses 0000h 0002h and 0003h 006ah of the lower block are reserved for the cpu reset vector and a set of interrupt vectors, respectively (see table 3). addresses 3fc0h 3fffh of the upper block are also reserved and cannot be accessed by the cpu. addresses 4000h ffffh are for external rom. when ea is low, the external rom must be used for all pro- gram addresses (0000h ffffh). figure 5 shows the data memory (ram) organization. the first 256 bytes are partitioned between two internal 128-byte blocks. the lower block (addresses 0000h 007fh) is used for registers or scratchpad memory and can be accessed either directly or indirectly (see the max7651/max7652 programmer s reference manual ). the upper block (addresses 0080h 00ffh) reflects a set of special function registers (sfrs) when accessed directly, and separate scratchpad memory when accessed indirectly. addresses 0100h ffffh are reserved for external ram. table 4 shows the sfr mapping to memory and table 5 shows the sfr contents on power-up or reset. unshaded register designations are consistent with the industry standard 8051. shaded register designations direct ram upper 128 bytes bank select lower 128 bytes 7fh ffh 00h ffh 80h 80h 7fh 2fh 1fh 17h 0fh 07h 00h 11 10 01 00 bit-addressable registers bank 3 bank 2 bank 1 bank 0 sfr space direct addressing indirect addressing lower 128 bytes direct and indirect addressing external interrupt vectors reset vector ffffh 3fffh 3fcoh 2000h 4000h reserved 1fffh 0000h upper internal ea = 1 3fffh 0000h 006ah 0001h 0002h 0000h external ea = 0 lower internal ea = 1 figure 4. program memory organization figure 5. data memory (ram) organization
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 18 ______________________________________________________________________________________ address range function natural priority* 0000h 0002h reset vector 0 interrupt vectors 0003h 000ah int0 (external interrupt 0) 1 000bh 0012h timer 0 2 0013h 001ah int1 (external interrupt 1) 3 001bh 0022h timer 1 4 0023h 002ah serial port 0 transmit/receive 5 002bh 0032h timer 2 6 0033h 003ah reserved 003bh 0042h serial port 1 transmit/receive 7 0043h 004ah flash memory write/page erase 8 004bh 0052h adc (end of conversion) 9 0053h 005ah reserved 10 005bh 0062h reserved 11 0063h 006ah watchdog timer 12 table 3. reset and interrupt vector locations hex address 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8 eip pwmc f0 b e8 eie eeal eeah eedat eestcmd e0 acc d8 eicon pwps pwda pwdb wdt d0 psw c8 t2con rcap2l rcap2h tl2 th2 c0 scon1 sbuf1 addat0 addat1 reserved adcon b8 ip reserved reserved b0 p3 version reserved reserved a8 ie a0 p2 98 scon0 sbuf0 90 p1 exif 88 tcon tmod tl0 th0 tl1 th1 ckcon reserved 80 p0 sp dpl0 dph0 dpl1 dph1 dps pcon table 4. sfr memory organization *lower priority number takes precedence. note 1: sfrs in column 0/8 are bit addressable. other sfrs are not bit addressable. note 2: the version sfr contains the silicon id and will change for future max7651/max7652 revisions.
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 19 register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p08011111111 sp8100000111 dpl0 82 00000000 dph0 83 00000000 dpl1 84 0 0 0 0 0 0 0 0 dph1 85 0 0 0 0 0 0 0 0 dps 86 0 0 0 0 0 0 0 0 pcon 87 00110000 tcon 88 00000000 tmod 89 00000000 tl08a00000000 th08b00000000 tl18c00000000 th18d00000000 ckcon 8e p19000000000 exif 91 0 0 0 0 1 0 0 0 scon0 98 00000000 sbuf0 99 00000000 p2a011111111 iea800000000 p3b011111111 ipb810000000 scon1 c0 0 0 0 0 0 0 0 0 sbuf1 c1 0 0 0 0 0 0 0 0 addat0 c2 0 0 0 0 0 0 0 0 addat1 c3 0 0 0 0 0 0 0 0 adcon c5 0 0 0 0 0 0 0 0 t2con c8 0 0 0 0 0 0 0 0 rcap2l ca 0 0 0 0 0 0 0 0 rcap2h cb 0 0 0 0 0 0 0 0 tl2 cc 0 0 0 0 0 0 0 0 th2 cd 0 0 0 0 0 0 0 0 pswd000000000 eicon d8 0 1 0 0 0 0 0 0 pwps da 0 0 0 0 0 0 0 0 pwdta db 0 0 0 0 0 0 0 0 pwdtb dc 0 0 0 0 0 0 0 0 wdt dd 0 0 0 0 0 0 0 0 table 5. sfr contents on power-up or reset
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 20 ______________________________________________________________________________________ are unique to the max7651/max7652. subsequent sections of this data sheet explain the sfr functions. reserved sfr addresses are used for max7651/ max7652 testing and should not be accessed by user software. undesignated sfr addresses are not imple- mented and will return indefinite data when read. special function registers for microprocessor operations and control accumulator sfr the accumulator sfr is used for arithmetic operations including addition, subtraction, multiplication, division, and boolean bit manipulation. accumulator specific instructions designate the accumulator as a . b sfr the b sfr is used for multiply and divide operations. it is otherwise available as a scratchpad register. program status word sfr the psw or program status word sfr contains bits that indicate the state of the microprocessor cpu. table 6 shows the individual bit functions. stack pointer sfr the sp or stack pointer sfr contains the top-of-the- stack address in internal ram. this address incre- ments before data is stored during push and call executions. the default value is 07h after reset, so that the stack begins at 08h. dual data pointer sfrs the max7651/max7652 feature dual data pointers to enhance execution times when moving large blocks of data. all dptr-related instructions use 16 bits con- tained at sfr pairs dph0 and dpl0 or dph1 and dpl1 to address external data ram or peripherals. bit 0 (sel) within the dps sfr determines the data pointer. no other bits have significance in this register. when sel= 0, dptr instructions use dph0 and dpl0, when sel=1, dptr instructions use dph1 and dpl1. program code developed for 8051 platforms that use a single data pointer (dph0 and dpl0) requires no modi- fication if sel = 0 (the default value). power control sfr the pcon power control sfr provides software con- trol over the power modes. in both idle and stop modes, cpu processing is suspended and internal registers maintain their current data. the stop mode additionally disables the internal clock and analog cir- cuitry. any enabled cpu interrupt can be used to termi- nate the idle mode. a reset is necessary to terminate the stop mode and is sufficient to terminate the idle mode. table 7 shows the pcon sfr format. instruction set the max7651/max7652 instruction set is compatible with the 8051 industry standard. see the max7651/ max7652 programmer s reference manual for a complete listing. analog-to-digital converter adc operation figure 6 shows a simplified model of the converter input structure and the associated switch timing. once initiated, a voltage conversion requires 224 periods of the external master clock. capacitor c hold charges to the difference between inputs ain+ and ain- during eight clock periods of acquisition time that begin on the rising edge of clock cycle 13. this charge sample is subsequently transferred to the adc (through the action of sw5) during eight clock periods that begin on the rising edge of clock cycle 21. the adc asserts a conversion complete flag on the rising-edge of clock cycle 225 (see adc special function registers ). register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acce000000000 eie e8 1 1 1 0 0 0 0 0 eeal ea 0 0 0 0 0 0 0 0 eeah eb 0 0 0 0 0 0 0 0 eedat ec 0 0 0 0 0 0 0 0 eestcmd ed 0 0 0 0 0 0 0 0 bf000000000 eip f8 1 1 1 0 0 0 0 0 pwmc fe 0 0 0 0 0 0 0 0 table 5. sfr contents on power-up or reset (continued)
since the acquisition time is limited to eight clock peri- ods, the acquired voltage at c hold can have signifi- cant error if the analog input source impedance (r s ) is large. limit the worst-case error to 1/2 lsb by ensuring, rs < 0.9 t clk / c hold where t clk is the clock period. smaller r s values may be necessary if an antialiasing filter is used. the adc continuously samples the positive and negative difference between the two external reference voltages ref+ and ref- by reconfiguring capacitor c ref over alternate eight clock-period intervals. switch pairs 1 and 2 are forced off and on, respectively, on the rising edge of clock cycle five to ensure synchronization with conver- sions. capacitor c hold also charges to the difference between ref+ and ref- on the rising edge of clock cycle 29 and remains charged until the next conversion. nevertheless, continuous c ref charging requirements dominate loading at the ref+ and ref- inputs. analog inputs the max7651/max7652 operate in either single-ended or differential mode. in single-ended mode, one of eight input channels (ain0 ain7) is assigned to ain+, and acom is assigned to ain- (see figure 6). in differential mode, the eight input channels are assigned to ain+ and ain- with four distinct pairings. table 6 shows the input assignments for different values of bits m3, m2, m1, and m0 in the a/d control sfr (see adc special function registers ). analog input protection inte rnal protection diodes clamp the analog inputs to av dd and agnd, so channels can swing within agnd - max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 21 sfr write clk 2 3 1 4 5 input sample 1 134 5 2 2 2.1pf v ref+ v ref+ v ref- ain- 3 4 ain+ 1.50pf v ref- c ref c hold figure 6. adc input structure and switch timing
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 22 ______________________________________________________________________________________ 0.3v and av dd + 0.3v without damage. for accurate conversions the inputs should not extend beyond the supply rails. transfer function figure 7 shows the bipolar two s complement adc transfer function. the single-ended conversion range extends from -v ref /2 to +v ref /2, where v ref = v ref+ - v ref- . the differential conversion range extends from -v ref to +v ref . each lsb in the single-ended and dif- ferential mode reflects voltage increments of v ref /4096 and 2v ref /4096, respectively. adc special function registers the adcon or a/d control sfr establishes adc oper- ating conditions and input configurations. table 7 shows the individual bit functions. a write to adcon initiates the a/d conversion process. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) smod0 gf1 gf0 stop idle bit name description 7 smod0 serial port 0 baud-rate doubler enable. smod0 = 1, doubles the baud rate. 6,5,4 reserved 3 gf1 general flag 1. general-purpose flag for software control. 2 gf0 general flag 0. general-purpose flag for software control. 1 stop stop mode select. stop = 1 stops the crystal oscillator and powers down the analog circuitry. 0 idle idle mode select. idle = 1 results in suspension of cpu processing. table 7. power control (pcon) format bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cy ac f0 rs1 rs0 ov f1 p bit name description 7cy carry flag. set to 1 , following an additional operation that results in a carry or a subtraction operation that results in a borrow. otherwise cleared to 0. 6 ac auxiliary carry flag. similar to cy, but used for bcd operations. 5 f0 user flag 0. general-purpose flag for software control. register select bits. these select one of four banks of eight registers that occupy the first 32 addresses in the lower internal ram. rs1 rs0 selected register bank 0 0 register bank 0, addresses 00h 07h 0 1 register bank 1, addresses 08h 0fh 1 0 register bank 2, addresses 10h 17h 4,3 rs1, rs0 1 1 register bank 3, addresses 18h 1fh 2ovover fl ow fl ag . s et to 1 , for any ar i thm eti c op er ati on that yi el d s an over fl ow . other w i se cl ear ed to zer o. 1 f1 user flag 1. general-purpose flag for software control. 0p parity flag. set to 1 , when the module 2 sum of the accumulator bits is one (odd number of 1 s), otherwise clear to zero (even number of 1 s). table 6. program status word (psw) format
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 23 external reference the max7651/max7652 require external reference volt- ages at v ref+ and v ref- . a single reference voltage can be used at v ref+, when v ref- is connected to agnd. the positive reference voltages must be no greater than the analog supply voltage av dd and capable of supplying 30a. bypass each reference voltage to agnd with a 0.1f capacitor in parallel with a 10f low esr capacitor. pwm digital-to-analog converters (dacs) the max7651/max7652 provide two pulse-width mod- ulated (pwm) dacs for applications that do not require high conversion accuracy. figure 8 shows the pulse- width-modulator block diagram. the clock signal is divided by 2 (x + 1), where x is the content of the pulse-width prescaler (pwps) sfr register. this reduced frequency signal is used to drive a modulo- 255 counter. when the counter value exceeds the value stored in sfrs pwda (output a) or pwdb md3 md2 md1 md0 mode ain+ ain- 0 0 0 0 single-ended ain0 acom 0 0 0 1 single-ended ain1 acom 0 0 1 0 single-ended ain2 acom 0 0 1 1 single-ended ain3 acom 0 1 0 0 single-ended ain4 acom 0 1 0 1 single-ended ain5 acom 0 1 1 0 single-ended ain6 acom 0 1 1 1 single-ended ain7 acom 1 0 0 0 differential ain1 ain0 1 0 0 1 differential ain3 ain2 1 0 1 0 differential ain5 ain4 1 0 1 1 differential ain7 ain6 1100 ref+ ref- table 8. analog input selection 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb 1lsb = v ref 4096 v in = (v ain ) - (v acom ) v ref = (v ref+ ) - (v ref- ) +fs = +v ref 2 -fs = -v ref 2 figure 7a. single-ended mode transfer function 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb v in = (v ain +) - (v ain - ) v ref = (v ref+ ) - (v ref- ) +fs = +v ref -fs = -v ref 1lsb = 2v ref 4096 figure 7b. differential mode transfer function
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 24 ______________________________________________________________________________________ (output b), the corresponding output transitions from low to high (figure 9). writing 00h to pwda or pwdb, yields a waveform with 100% duty cycle (high), and writing ffh to pwda or pwdb yields a waveform with 0% duty cycle (low). writing an intermediate register value y, yields a wave- form with duty cycle (1 - y / 255) ? 100%. tables 10, 11, and 12 show the formats of the pwps, pwda, and pwdb sfr s. external low-pass filters are needed to obtain dc volt- ages between 0 and dv dd from the pwm outputs. simple rc filters are preferred. choose r >2k ? to avoid excessive loading, and choose c <0.1f to avoid large transient currents that reflect the pwm switching action. each filtered pwm output can source or sink up to 2ma. do not exceed this specification. if larger out- put capability is required, provide an appropriate buffer such as a unity-gain op amp. pwm circuitry and pwm outputs a and b are enabled with the pulse-width modulator control (pwmc) sfr. table 13 shows the pwmc sfr format. watchdog timer the max7651/max7652 features a watchdog timer that resolves irregular software control. the watchdog timer resets the microprocessor if software fails to reset the timer within one of four pre-selected time intervals. the timer generates an optional interrupt after 2 16 , 2 19 , 2 22 , or 2 25 clock periods of the external oscillator. it gener- ates the reset signal after an additional 512 clock peri- ods. table 14 indicates specific interrupt and reset times that apply for a 12mhz clock frequency. five watchdog-related control bits and two status flags are located in different special function registers. table 15 shows the particular functions and sfr locations. 8051-compatible peripherals parallel i/o ports like other 8051-based systems, the max7651/ max7652 features four 8-bit parallel ports that support general input and output, address and data lines, and various special functions. each bidirectional port has a latch register (sfrs p0, p1, p2, and p3), an input buffer, and an output driver. port p0 is open-drain. writing a logic level 1 to a p0 pin establishes a high-impedance input. when used as a general-purpose output, a p0 pin requires an external pull-up resistor to validate a logic level 1. when used as an address/data output, a p0 pin features an internal active high driver. port 0 is a bidirectional flash data i/o port during flash programming and verification. port 1: port 1 is a bidirectional i/o port with internal pullups. port 1 pins that have 1 s written to them are pulled high by the internal pullups and can serve as inputs. port 1 receives low-order address bytes during flash programming and verification. port 2: port 2 is a bidirectional i/o port with internal pullups. port 2 pins that have 1 s written to them are pulled high by the internal pullups and can serve as inputs. port 2 also serves as the high-order address and data bus (for 16-bit operations) during accesses to external memory, using strong internal pullups when emitting 1 s. port 3: port 3 is a bidirectional i/o port with internal pullups. port 3 pins that have 1 s written to them are pulled high by the internal pullups and can serve as inputs. the p1 and p3 ports support the special functions list- ed in table 16. write a 1 to the corresponding bit in the port register to enable the alternative function. user accessible sfr register user accessible sfr register user accessible sfr register sfr pwda register modulo 255 counter pwma output pwmb output pwps from crystal oscillator sfr pwdb register magnitude comparator >= magnitude comparator >= divide by two figure 8. pwm block diagram tpw high tpw period tpw period = 2(pwps+1) 255/f osc tpw high = (255 - pwd(x))/255 tpw period f osc = crystal frequency of x1, x2 pins figure 9. pwm output waveform
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 25 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) bit 3 bit 2 bit 1 bit 0 0 0 0 0 table 11. a/d data-0 (addat0) format sfr address c2h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pwps7 pwps6 pwps5 pwps4 pwps3 pwps2 pwps1 pwps0 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pwda7 pwda6 pwda5 pwda4 pwda3 pwda2 pwda1 pwda0 table 13. pulse-width data a (pwda) format sfr address dbh bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) sign bit bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 table 10. a/d data-1 (addat1) format sfr address c3h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cc ccvt ccie ovrn m3 m2 m1 m0 bit name description 7cc conversion complete flag (read only). the max7651/max7652 set this flag to 1 following a conversion to indicate valid data in the addat1 and addat0 data sfrs (see below). the cc bit is cleared to 0 when addat1 is read by the cpu. 6 ccvt continuous conversion enable (read/write). when ccvt = 1, the adc performs continuous conversions at the rate of 224 clock cycles/conversion. conversions continue until the max7651/ max7652 is reset or until ccvt is cleared, in which case conversions stops after the current conversion ends. 5 ccie conversion complete interrupt enable (read/write). when ccie = 1, interrupt 3 is generated at the end of each conversion. 4 ovrn overrun flag (read only). the max7651/max7652 set this flag to 1 whenever a conversion completes while cc is set. the previous conversion result is overwritten. the ovrn bit is cleared to 0 when addat1 is read by the cpu. 3 0m3 m0 analog input multiplexer select bits. used to establish input configurations for single-ended or differential conversions (see table 6). table 9. a/d control (adcon) format sfr address c5h note: sfrs addat1 and addat0 contain the results of individual a/d conversions with the formats shown in tables 8 and 9. a read to addat1 clears the cc and ovrn flags in adcon. table 12. pulse-width prescaler (pwps) format sfr address dah
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 26 ______________________________________________________________________________________ wd1 wd0 interrupt timout time (ms) reset timout time (ms) 00 2 16 clocks 5.461 2 16 + 512 clocks 5.474 01 2 19 clocks 43.691 2 19 + 512 clocks 43.734 10 2 22 clocks 349.525 2 22 + 512 clocks 349.567 11 2 25 clocks 2796.000 2 25 + 512 clocks 2796.042 table 16. watchdog interrupt and reset times (f ck = 12mhz) serial interface ports the max7651/max7652 each have two serial inter- faces that operate according to the 8051 industry stan- dard. serial port 0 uses sfrs scon0 and sbuf0 for control and buffer functions. serial port 1 uses sfrs scon1 and sbuf1 with identical bit functionality. see the max7651/max7652 programmer s reference manual for details concerning serial-port data opera- tions and timing information. timers/counters the max7651/max7652 have three timer/counters that function in several different modes for applications such as uart baud-rate control. all three timer/coun- ters operate according to the 8051 industry standard. specifically, the control (tcon), mode (tmod), timer-0 parameter (tl0, th0), timer1 parameter (tl1, th1), and timer-2 parameter (tl2, th2, rcap2l, rcap2h) sfrs have conventional formats. see the max7651/ max7652 programmer s reference manual for informa- tion concerning timer/counter applications. crystal oscillator the max7651/max7652 each have a single-stage invert- er (input at xtal1, output at xtal2) that supports a crys- tal controlled oscillator. the crystal oscillator frequency should be between 1 and 12 mhz. note: external flash memory programming requires a minimum crystal oscillator frequency of 4mhz. rs(typ) 25 40 ? rs(max) 150 ? load capacitance 10 15pf oscillation mode fundamental frequency 12,000mhz (max) tolerance 0.01% holder capacitance 3pf motional inductance (typ) 50mh motional capacitance (typ) 0.0035pf crystal specification: bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pwdb7 pwdb6 pwdb5 pwdb4 pwdb3 pwdb2 pwdb1 pwdb0 table 14. pulse-width data b (pwdb) format sfr address dch bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pwon pwena pwenb bit name description 7 pwon pulse-width-modulator enable. set pwon to 1 to enable the divide-by-two, pwps prescaler, and modulo-255 counter circuit functions. 6 2 not used 1 pwena pwm output a enable. set to 1 to enable pwm output a. 0 pwenb pwm output b enable. set to 1 to enable pwm output b. table 15. pulse-width-modulator control (pwmc) format sfr address feh
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 27 an external oscillator can also be used to clock the max7651/max7652 at frequencies between 1 and 12mhz, provided that the duty cycle is between 40% and 60%. when using an external clock source connect the clock to xtal1, with xtal2 unconnected. applications information performing a conversion an example of a conversion with the max7651/ max7652 is as follows: write to the adcon sfr, setting bit ccie to 1, and bits m3 m0 to appropriate values for the desired dif- ferential or single-ended analog input configuration (tables 6 and 7). wait 224 clock cycles to receive interrupt 3 as an indication that the a/d conversion is complete. read the conversion data in sfrs addat0 and addat1 as described in tables 8 and 9. using flash memory the upper and lower 8kb blocks of internal flash mem- ory are each organized as 128 64-byte pages. read, write, and page-erase operations cannot be applied to either block while executing program commands from the other block. note: standard movc operations are supported. flash memory special function registers tables 17 and 18 show the formats for the eeah and eeal sfrs. the eeah register specifies the applicable flash memory block (high or low) and the page address within that block. the eeal register specifies the byte address within the specified page. table 19 shows the format for the flash memory data (eedat) sfr that is used for 8-bit read and write trans- fers from and to a specified address. table 20 shows the format for the flash memory status and command (eestcmd) sfr. bits rdyhi and rdylo are cleared to zero when a read, write, or page- erase operation is applied to the high or low flash mem- ory block. these bits are set to one once the flash name sfr bit description wdif eicon 3 watchdog interrupt flag. wdif is set to 1 after completion of the interrupt timeout period (see table 14). wdif must be cleared by software before exiting interrupt service routine. otherwise interrupt reoccurs upon exiting. wdif is automatically cleared by either an external rst assertion or a wdt-generated reset. wtrf wdt 2 watchdog reset flag. the wtrf bit is a status/control bit indicating that the watchdog counter has counted an additional 512 clocks past the wdt interrupt and has generated a processor reset. the 8051 s reset routine should check the wtrf flag to determine the source of the reset. additionally, if the wtrf flag has been set the watchdog timer counts will be reset when a zero is written to the wtrf flag. this allows the processor to regain synchronization with the wdt after a wdt reset has occurred. wtrf is also cleared when a zero is written to it. ewt eicon 1 enable watchdog timer. set to 1 to enable the watchdog timer. an assertion at the external rst pin automatically clears ewt. if ewt is cleared after being set. the watchdog timer count will suspend until ewt is set to 1 again. rwt eicon 0 reset watchdog timer. writing a 1" to the rwt bit will reset the watchdog counter only if the end of the count has been reached (wdif = 1) and the 512 clock window has not expired (wtrf = 0). writing to rwt before the timeout period will not reset the watchdog timer . wd1 ckcon 7 watchdog control bit 1. controls the watchdog interrupt timeout (see table 14). wd0 ckcon 6 watchdog control bit 0. controls the watchdog interrupt timeout (see table 14). ewdi eie 4 enable watchdog interrupt. an interrupt will be generated after the interrupt timeout period when ewdi = 1. either a wdt-generated reset or an assertion at the external rst pin automatically clears ewdi. table 17. watchdog timer control and status bits
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 28 ______________________________________________________________________________________ bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) eeal5 eeal4 eeal3 eeal2 eeal1 eeal0 bit name description 7,6 not used. 5 - 0 eeal_ byte within page address bit. determines the byte address within a flash memory page. eeal5 is the msb. table 20. flash address low (eeal) format sfr address eah bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) block eeah6 eeah5 eeah4 eeah3 eeah2 eeah1 eeah0 bit name description 7 block flash memory block. set block = 1 to access the high flash memory block. set block = 0 to access the low flash memory block. 6 - 0 eeah_ page address. determines the flash memory page. eeah6 is the msb. table 19. flash address high (eeah) format sfr address ebh memory operation is complete. never attempt to exe- cute a flash memory command when either rdyhi or rdylo are 0 (command action in progress). flash memory read to read flash memory, load the address into sfrs eeah and eeal. then write aah to eestcmd. the results of the read operation will be available in sfr eedat in the next cpu instruction cycle. flash memory write erase operations set all bits to 1 . after a byte has been programmed it must be erased before it is re-writ- ten. to write to flash memory, load the address into sfrs eeah and eeal, and load the data into eedat. then write 55h to eestcmd. the execution time for flash memory write is 63s (typ) and is independent of the cpu clock. port pin alternative function description p1.3 txd1 transmit serial output for serial port p1.2 rxd1 receive serial input for serial sort p1.1 t2ex timer 2 external capture/reload trigger p1.0 t2/t2_out timer 2 external input/output p3.7 rd read output p3.6 wr write output p3.5 t1 timer 1 external input p3.4 t0/ready timer 0 external input/ready state output (external flash programming mode only) p3.1 txd0 transmit serial output for uart 0 p3.0 rxd0 receive serial input for uart 0 table 18. alternate port functions
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 29 note: do not write to the same location more than twice before the next page/mass erase operation. flash memory page erase the page erase operation sets all bits within the page to 1 s. to erase a page from flash memory, load the page address into sfr eeah, register eeal is not used. then write 5ah to eestcmd. the execution time for page erase is 9.4ms (typ) and is independent of the cpu clock. note: do not attempt to apply read, write, or page- erase operations to the flash memory block in which the cpu is currently executing program instructions. external flash memory programming the max7651/max7652 are normally shipped with the internal flash memory blocks fully erased (all bits set to 1) and ready for external programming. external write, read (verify), and mass-erase operations are available. flash memory addresses for either the upper or lower 8-kbyte blocks are specified at ports 1 and 2. before applying any external flash memory operations, power-up the max7651/max7652 with rst asserted. ale, psen , and ports p1 p3 are pulled high with weak resistive pullups. port p0 requires 10k ? external pull- ups. wait at least 10ms for the oscillator and internal circuitry to stabilize. the program, verify and mass- erase flash memory programming steps are outlined below. note: failure to follow proper power-up conditions or the specified flash memory programming steps can result in loss of flash data integrity. external flash memory program (table 2) erase operations. set all bits to 1 . after a byte has been programmed it must be erased before it is re-written. 1) power-up the device with rst asserted and allow ale and psen to float to the 1 state (they will be internally pulled-up during rst assertion). 2) wait 10ms for the internal bandgap and oscillator to stabilize. 3) apply the memory location on the address lines at ports 1 and 2. 4) apply data to the data lines at port 0. 5) raise ea / v pp to dv dd and pull psen low. 6) set p2.6, p2.7, p3.6, and p3.7 to the levels shown in table 2. 7) set p2.5 low or high for the lower or higher 8kb flash memory block. 8) force ale / prog low. p3.4 (ready) will go low to indicate a write in progress. 9) when p3.4 returns high (write complete after approximately 63s), set ale / prog high. 10) power-down sequence. a) remove drive from and allow psen and ale/ prog to float high. b) pull ea low. c) high-z all digital pins. d) remove power from all power pins. note: do not write to the same location more than twice before the next page/mass erase operation. external flash memory verify (table 2) external verify: if lock bits lb1 and lb2 have not been programmed, the programmed flash array(s) can be read back through the address and data lines for verification. the lock bits cannot be verified directly. verification of the lock bits is achieved by observing that their features are enabled. external verify (readback) power-up sequence: 1) power-up the max7651/max7652 with rst assert- ed, allow ale and psen to float to the 1 state (they will be internally pulled-up during rst assertion). wait 10ms for the internal bandgap and oscillator to stabilize. 2) pull psen low, ea high, ale high, and set p2.6, p2.7, p3.6, p3.7, p2.5, as per flash programming modes (table 2) for reading either lower or upper flash memory block. note: p2.7 is cycled low/high to perform a flash read operation. minimum low time for p2.7 is ten clock cycles. external verify power-down sequence: 1) power-down sequence a)remove drive from and allow psen and ale/ prog to float high. b) pull ea low. c) hi-z all digital pins. d) remove power from all power pins.
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 30 ______________________________________________________________________________________ external flash memory mass erase a mass erase operation sets all bits, including the lock bits to 1 (table 22). external erase: both flash arrays can be simultaneously mass-erased electrically by using the proper combination of control signals as shown in table 2. the erase operation must be executed before either memory can be pro- grammed. lock bits are also erased (set to 1). external chip erase power-up sequence: 1) power-up chip with rst asserted, and allow ale and psen to float to the 1 state (they will be inter- nally pulled-up during rst assertion). wait 10ms for the internal bandgap and oscillator to stabilize. 2) pull psen low, ea high, set p2.6, p2.7, p3.6, p3.7, and p2.5, as per mass erase mode in the flash programming modes (table 2). 3) p3.4 will be low during mass erase cycle and return hi at the end of mass erase cycle. external chip erase power-down sequence: 1) power-down sequence a)remove drive from and allow psen and ale/ prog to float high. b) pull ea low. c) hi - z all digital pins. d) remove power from all power pins. figure 2 shows the timing waveforms that apply for the flash memory mass erase operation. flash memory lock bits the max7651/max7652 each contains three lock bits which can be left unprogrammed (logic 1 ) or can be programmed (logic 0 ) to obtain the additional fea- tures listed in the table below: when lock bit 1 is programmed (set to logic 0 ), the logic level at the ea pin is sampled and latched during rst deassertion. subsequent changes in logic levels on ea have no effect. if the device is powered-up with- out a reset (rst), the latch initializes to a random value and holds that value until rst is pulsed high, then low. it is necessary that the latched value of ea be in agree- ment with the current logic level at that pin in order for the device to function properly. signature bytes the max7651/max7652 contain three signature bytes with the information shown in table 23. read each byte by following the flash memory read procedure, but set p2.6, p2.7, p3.6, and p3.7 at low. signature bytes are not affected by mass erase or page erase operations. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 table 21. flash memory data (eedat) format sfr address ech bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdyhi/ eecmd7 rdylo/ eecmd6 eecmd5 eecmd4 eecmd3 eecmd2 eecmd1 eecmd0 bit name description 7 rdyhi high block ready status. the max7651/max7652 set rdyhi to 0 during read, write, and page- erase operations that are applied to the 8-kbyte high block of flash memory. the bit is otherwise set to 1. 6 rdylo low block ready status. the max7651/max7652 set rdylo to 0 during read, write, and page- erase operations that are applied to the 8-kbyte low block of flash memory. the bit is otherwise set to 1. 7 - 0 eecmd flash memory command bits. used to specify read, write, or page-erase memory commands. eecmd7 is the msb. table 22. flash status and control (eestcmd) format sfr address edh
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 31 interrupt system the max7651/max7652 has ten program-assist inter- rupts that are either external or internal to the 8051 sys- tem. table 24 shows the sfr bit locations for interrupt enable and priority control. shaded table regions reflect the 8051 industry standard. set sfr bit ie.7 high to enable all interrupts. see the max7651/max7652 programmer s reference manual . timers the max7651/max7652 feature several modes of tim- ing control through the ckcon special function regis- ter. table 25 shows the ckcon sfr format. the individual control bits can be used to set the number of clock cycles needed (four or twelve) to increment each timer/counter or the number of clock cycles needed to execute the movx instruction. see the max7651/ max7652 programmer s reference manual for further details. analog and digital supplies the max7651/max7652 have multiple power-supply inputs: one analog av dd and three digital dv dd . the pulse width modulators have their own power supply inputs, pwmv and pwmg. decouple all supply inputs with a 0.1f capacitor in parallel with a 10f low esr capacitor, with both capacitors as close to the supply pins as possible and with the shortest possible connec- tion to the ground plane. parameter min max comments t progl 10t ck t progl must equal t write during lockbit writes t asuw 3t ck t write 7t ck + 54 s7t ck + 72 s t adsur 3t ck t read 8t ck + 50ns read access time t p27l 10t ck t p27h 3t ck t ck 83ns 250ns table 23 note: p2.6, p2.7, p3.6, and p3.7 must also meet t asuw (min) timing specification. program lock bits lb1 lb2 lb3 protection type 1 1 1 1 no program lock features (default after a mass erase) 2011 movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset (rst), and further external data programming of both flash arrays is disabled. 3 0 0 1 verify (read) is disabled. (see mode 2) 4 0 0 0 external execution is disabled ( ea override, see mode 3). table 24. lock bit protection modes address data meaning 30h 7fh jedec continuation byte 31h cbh manufactured by maxim 32h 20h max7651/max7652 table 25. max7651/max7652 signature bits
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems 32 ______________________________________________________________________________________ power requirements max7651 operates from +5v while the max7652 oper- ates from +3v analog and digital supply voltages. the analog supply current is typically 2ma. the typical digi- tal supply currents (continuous a/d conversions at 12mhz clock frequency) are 5ma and 13ma at +3v and +5v, respectively. current consumption will vary depending on ram read/write and flash read/write page erase duty cycle. idle mode in idle mode, cpu processing is suspended and inter- nal data registers maintain their current data. however, unlike typical 8051 systems, the clock is not disabled internally. set pcon.0 (idle) high to enter the idle interrupt associated feature enable sfr bit (note 2) priority sfr bit (note 3) priority int0 external interrupt 0 ie.0 ip.0 1 int1 external interrupt 1 ie.2 ip.1 3 flash flash operation complete eie.0 eip.0 8 adc a / d operation complete eie.1 eip.1 9 wdti watchdog timer eicon.1 eip.4 10 tf0 or exf0 timer 0 ie.1 ip.1 2 tf1 or exf2 timer 1 ie.3 ip.3 4 ti_0 or ri_0 serial port 0 ie.4 ip.4 5 tf2 or exf2 timer 2 ie.5 ip.5 6 ti_1 or ri_1 serial port 1 ie.6 ip.6 7 table 26. max7651/max7652 interrupts (note 1) note 1: shaded areas reflect the 8051 industry standard. note 2: set enable sfr bit high to enable interrupt. note 3: set priority sfr bit high to eatablish high priority. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) wd1 wd0 timer2 timer1 timer0 md2 md1 md0 bit name description 7 wd1 6 wd10 set wd1 and wd0 to adjust the interrupt interval for the watchdog timer. (see watchdog timer .) 5 timer2 timer 2 control. set timer2 = 1 for timer2-associated counter increments at four clock intervals. set timer2 = 0 for increments at 12 clock intervals. 4 timer1 timer 1 control. set timer1 = 1 for timer1-associated counter increments at four clock intervals. set timer1 = 0 for increments at 12 clock intervals. 3 timer0 timer 0 control. set timer0 = 1 for timer0-associated counter increments at four clock intervals. set timer0 = 0 for increments at 12 clock intervals. 2 md2 1 md1 0 md0 set md2, md1, and md0 to adjust the read/write strobe width (in clocks). the number of clock cycles is two plus the md2, md1, md0 decimal value. md0 is the lsb. table 27. ckcon sfr address 8eh
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 33 mode after the instruction is complete. figure 10 shows the related timing characteristics. enable any interrupt to clear pcon.0 and exit the idle mode (see figure 11 for the related timing). assert rst alternately. stop mode in stop mode, the internal clock and analog circuitry are powered-down. set pcon.1 (stop) high to enter the stop mode after the instruction is complete. figure 12 shows the related timing characteristics. the only way to exit stop mode is to assert rst. definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the max7651/max7652 are mea- sured using the best straight-line fit method. into clk ale ~psen mem addr idle address of last executed instruction 003h figure 11. idle mode exit timing clk ale -psen mem addr idle pcon.0 n n + 1 figure 10. idle mode entry timing
max7651/max7652 differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset points. for an adc, the offset point is the midstep value when the digital output is zero. gain error the gain or full-scale error is the difference between the ideal and actual gain points on the transfer function, after the offset error has been canceled out. for an adc the gain point is the midstep value when the digi- tal output is full-scale. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, snr is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise including thermal noise, reference noise, clock jitter. therefore, snr is computed by taking the ratio of the rms signal to the rms noise which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) signal-to-noise plus distortion is the ratio of the funda- mental input frequency s rms amplitude to rms equiv- alent of all other adc output signals. sinad (db) = 20 x log (signal rms / noise rms ) effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. with an input range equal to the full-scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmon- ics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v2 through v5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the fundamental maximum signal component to the rms value of the next largest distortion component. thd vvvv v = +++ () ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log flash programmable 12-bit integrated data-acquisition systems 34 ______________________________________________________________________________________ cpu cycle clk ale ~psen mem addr stop pcon.1 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 n n + 1 n + 2 figure 12. stop mode timing chip information transistor count: 358,000 process: cmos
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems ______________________________________________________________________________________ 35 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 ref+ test 64-tqfp top view dv dd dgnd xtal1 xtal2 rst ea /v pp p1.7/ad7 p1.6/ad6 p1.5/ad5 52 53 49 50 51 p1.4/ad4 p1.3/txd1/ad3 p1.2/rxd1/ad2 p1.1/t2ex/ad1 p1.0/t2/t2out/ad0 t1 /p3.5 wr /p3.6 rd /p3.7 p3.3 ready/t0/p3.4 txd0/p3.1 p3.2 dgnd rxd0/p3.0 a8/p2.0 dv dd a10/p2.2 a9/p2.1 a11/p2.3 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 dv dd dgnd ale/ prog 33 34 35 36 37 psen p2.7 p2.6 p2.5 p2.4/a12 agnd av dd ain7 ain6 ain5 pwmb pwma pwmg pwmv ref- ain4 ain3 ain2 ain1 48 p0.7/ad7 ain0 64 acom 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max7651 max7652 int0 int1 pin configuration
max7651/max7652 flash programmable 12-bit integrated data-acquisition systems maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information 64l, 10x10x1.4 tqfp.eps

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